IJEA - Volume 6 Issue 2 (February2017)

 


Sr/No/ Title Pdf
1 Implementation of High Speed and Area Optimised dual IDEA Key Encryption using VHDL
Neelam Soni, Shivam Solanki

Abstract-Thesis work proposed a new 2^n+1 modulo multiplier for dual key IDEA encryption in the design which generates less number of partial products (≤ n 2) and the less area at very high speed. The multiplication is based on Wallace tree along with specialized shifting. Coding with different combinations of eight rounds is been done at gate level i.e. fully dataflow modeling style for high throughput.. New modulo multiplication is been proposed in which multiple patterns can be done with less area. The string matching module is coded and functionally verified using VHDL language targeting Virtex IV pro FPGA and performance measures in terms of speed and resource utilization. Our work is mainly based on designing an efficient architecture (IP) for a cryptographic module for secure data trafficking and a network intrusion detection system for a high speed network. The complete designs are coded using VHDL language and are verified using Xilinx- ISE simulator for verifying their functionality.

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2 Design of high speed and less area RNS based FIR filter using HDL
Shivam purwar, Deepika soni

Abstract-Digital filters are important things in Very Large Scale Integration (VLSI) designs. The available Finite Impulse Response (FIR) filter process a long transient response which considers as its major limitation. To get over this problem, Residue Number System (RNS) based FIR filters is been proposed which is explains in this paper. Highspeed is determined by using the residue arithmetic way that allows the computation for filter output by using N FIR sub filters for reduced dynamic range working in parallel form. Total three Moduli 2n-1, 2n, 2n+1 sets are used in proposed RNS based Filter. 4-tap Low Pass Filter (LPF) type for FIR filter and RNS based FIR filter along with 4-tap LPF are designed. Verilog HDL language is used for RTL entry and analyzed in this paper. The simulation is done using Xilinx EDA tool Integrated Simulation Environment ISE-12.2

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